The Role The Synopsys Verification R&D team in Herzelia, Israel is part of a worldwide R&D team responsible for the development of simulation, emulation and formal verification software products.
Synopsys is seeking a creative, ambitious and talented engineer to fill an R&D Engineer Intern role in the Emulation team in Israel.
Key responsibilities:
• Development of C/C++ code that implements requested functionality • Analysis and fixing of bugs in the emulation and simulation products • Writing technical documentation and presentations on developed functionality
The ideal candidate will have:
• A relevant degree in electronic engineering or software engineering . Familiarity with Verilog hardware description language and verification methodologies - advantage • Basic knowledge of ASIC and FPGA design flows is desirable. • Has strong desire to learn and explore.
If you wish to apply for this position please click on the following link: